Integrated chips contain millions of transistor devices. Transistors are connected to off chip electronics by way of a series of metal interconnects, which couple the transistor devices to a package (e.g., to a leadframe of a package). The metal interconnects comprise metal layers that progressively increase in size as they get further away from the transistor devices. Typically, the lowest metal layer comprises a contact (e.g., a W contact) that vertically connects a transistor device (e.g., a polysilicon layer or a well of a transistor) to a first metal interconnect layer that runs parallel to the surface of the integrated chip.
In SRAM memory cells, butted contacts are widely used to connect one or more transistor devices (e.g., a polysilicon layer, a well layer) to a first metal interconnect layer. Butted contacts are large contacts that enable connection of one or more gates (e.g., comprising a polysilicon material) to one or more active areas (i.e., diffusion regions) without the use of a horizontal metal interconnect layer. By using a single butted contact to connect to a gate and an active area, the size of an SRAM memory cell can be reduced.